Recently, the number of functions of an electronic instrument has increased, and characteristics of its power source being necessary for these functions have become varied; therefore, many kinds of power sources are required for the electronic instrument. Consequently, as shown in FIG. 8, a so-called system power source is being used, in which plural constant-voltage circuits REGX1 through REGXn (n is an integer where n>1) are integrated on one chip, power is supplied from the constant-voltage circuits REGX1 through REGXn to corresponding loads Lo1 through Lon, and each of the constant-voltage circuits REGX1 through REGXn is controlled totally by a control circuit (not shown):
FIG. 9 is a diagram showing a circuit example of one of the constant-voltage circuits REGX1 through REGXn shown in FIG. 8. Since each of the constant-voltage circuits REGX1 through REGXn has the same structure, in FIG. 9, an arbitrary constant-voltage circuit REGXk (k=1 to n) is shown.
The constant-voltage circuit REGXk consists of a reference voltage generating circuit REFk, an error amplifying circuit APk, a transistor for controlling output voltage PBk, and resistors for detecting output voltage RXk and RYk, and outputs a generated output voltage Vok to a corresponding load Lok.
The reference voltage generating circuit REFk consists of a depletion-mode NMOS transistor NAk and an enhancement-mode NMOS transistor NBk (hereinafter, an enhancement-mode NMOS transistor is simply referred to as an NMOS transistor and an enhancement-mode PMOS transistor is simply referred to as a PMOS transistor). In the depletion-mode NMOS transistor NAk, the drain is connected to a power source Vdd, and the gate and the source are connected; therefore, the drain current of the depletion-mode NMOS transistor NAk becomes a constant current when the voltage between the gate and the source of the depletion-mode NMOS transistor NAk Vgs equals to 0.
To the source of the depletion-mode NMOS transistor NAk, the drain of the NMOS transistor NBk is connected, and in the NMOS transistor NBk, the source is connected to ground voltage, and the gate is connected to the drain. Therefore, the drain current of the NMOS transistor NBk becomes equal to the drain current being the constant current of the depletion-mode NMOS transistor NAk. From this, the gate voltage of the NMOS transistor NBk is determined by the drain current of the depletion-mode NMOS transistor NAk, and this voltage becomes a reference voltage Vrefk which is output from the reference voltage generating circuit REFk.
The error amplifying circuit APk controls the operation of the transistor for controlling output voltage PBk so that a voltage VXk, which is the output voltage Vok divided by the resistors for detecting output voltage RXk and RYk, becomes the reference voltage Vrefk.
In the system power source, in a case where 20 or more constant-voltage circuits are formed on one chip, if a bias current setting circuit and a reference voltage generating circuit are provided in each constant-voltage circuit, there is a problem in which the entire area of the semiconductor chip becomes large. In order to solve this problem, a bias current source circuit for supplying bias currents to many analog basic circuits is disclosed (for example, refer to Patent Document 1) in which a PMOS transistor and an NMOS transistor are connected in series between a power source voltage and ground voltage, the power source voltage is divided by this series circuit, and gates of many NMOS transistors and PMOS transistors are connected to this divided voltage.
[Patent Document 1] Japanese Laid-Open Patent Application No. 8-321731
However, the characteristics of the MOS transistor change due to a variation in its manufacturing process and a difference of chip positions in one wafer. Consequently, there is a problem in which bias current values to NMOS transistors NCk and NDk being a differential pair of the error amplifying circuit APk and to a PMOS transistor PEk being an output stage of the error amplifying circuit APk in FIG. 9 are greatly dispersed. In addition, the dispersion of the drain current at the time of 0 bias of the depletion-mode NMOS transistor NAk is as large as −50% to +100%. Further, the dispersion of the temperature characteristic is ±20 to 30% in the using temperature range (−30° C. to 85° C.). Due to these, the reference voltage Vrefk to be output from the reference voltage generating circuit REFk and the drain current of the NMOS transistor NBk are changed largely caused by the variations of the manufacturing process and the temperature. Further, the characteristics of the reference voltage generating circuit REFk are changed and also the reference voltage Vrefk is changed. These are problems. Since the change of the reference voltage Vrefk directly affects the change of the output voltage Vok, the resistance ratio between the resistors for detecting output voltage RXk and RYk is required to be adjusted by trimming and so on.
In the system power source, there is a case in which 20 or more constant-voltage circuits are provided on one chip, and when the value of the bias current of the error amplifying circuit included in each constant-voltage circuit and the value of the constant-current load are greatly dispersed, a problem occurs in which the current consumption of the system power source exceeds its specification. In addition, since the amount of phase compensation of the error amplifying circuit is changed by the bias current value, a problem occurs in which the most suitable phase compensation is not executed. Further, since the change of the bias current causes the change of the various characteristics to be required for the constant-voltage circuits such as a ripple eliminating ratio, an input voltage response characteristic, and an output voltage response characteristic, it is necessary that the bias current be in a predetermined current value range in order to obtain the characteristics in its specifications.